Mapped digital signals are frequently employed in the testing of memory devices. To better understand how digital signals are mapped and the purpose of mapping, it is convenient to begin with a review of an application of mapped digital signals, specifically, the testing of memory devices.
Reliable data storage and retrieval is a valuable characteristic of electronic devices and systems. Where the device or system has the capability to store a multiplicity of independent data bits, rigorous tests are often employed during manufacturing to ensure independent storage and retrieval. It is common in a defective storage device or system that a write operation to a first addressed location erroneously affects data in a second location that is expected to be independent of the first. Similarly, a read operation that is expected to retrieve data written to a first location may be unsuccessful. An unsuccessful read operation may have retrieved data from an unexpected location or the data may have been affected by other data physically located close to the storage location being read.
In systems capable of storing a large quantity of data, exhaustive tests of every possible read failure mechanism are impractical. However, a wide majority of defects can be identified by so called pattern tests. The most popular memory pattern tests include stripe and checkerboard patterns. These patterns are developed to exercise a cell by storing data in the tested cell that is of an opposite logic state from the data stored in cells physically surrounding the tested cell or related control circuits. The test pattern designer develops a test pattern with knowledge of the physical arrangement of cells in the device or system, knowledge of the row and column addresses identifying each cell, and knowledge of the electrical conditions corresponding to logical data values stored. Taken together, this knowledge is called the topology of the memory device or system.
Once a pattern test has been written, it is desirable to use that pattern test on a variety of devices and systems as well as a variety of test equipment. Translation is required because not all devices and systems to be tested have the same topology. A memory device having an addressable array of rows and columns of cells is said to have a topology that relates the physical location of the cell to the logical number of the row and column used to address that cell. Some devices are physically arranged with odd numbered rows physically adjacent to each other and even numbered rows physically adjacent to each other forming two separate sections of the device. Other devices interleave the rows by a multiple, for example by 1 for consecutive rows or by 4 for groups of rows. Similarly, columns could be interleaved in any manner. The data representation in a cell may be a logic high in one section of the array and a logic low in an adjacent cell for the same logic state being stored. These three variations of topology are collectively called topological maps.
A standard pattern test can be translated using topological maps so that the pattern test relates properly to a particular device under test. If the topological mapping is incorrect, the effectiveness of the test may be compromised. For example, if a topological map that specified that consecutively addressed rows were physically adjacent was used to test a device having odd numbered rows located in a first section of the device and even numbered rows located in a second section of the device physically removed from the first, then a stripe test designed to write and read back opposite data in consecutive rows would not properly stress the memory device. In addition to memory device characteristics, topological translation may also be dependant on the make and model of the tester being used to execute the pattern test.
Existing methods for verifying topological translation definitions (signal mapping) are unsatisfactory. As an example, consider a dynamic random access memory manufacturing facility that uses two different models of dynamic random access memory testers for the same product line. If the rate of detecting defective memory devices on the first tester is higher than the rate of detecting defective memory devices on the second tester, then there is reason to suspect that the second tester's test method is defective in some way. The second tester could be analyzed using a memory that was intentionally manufactured with a known defect. However, manufacture of such a memory could be costly when normal manufacturing is fully automated. As a second strategy, a test fixture that was designed to exhibit a defect could be built. However, the cost of manufacturing a test fixture is high and the choice of defects that can be designed into the test fixture is limited. As a third strategy, a fully functional memory could be intentionally damaged to cause an intended defect. Again, the choice of possible defects is limited. Finally, a strategy wherein the pattern test software is modified to fail to refresh a location or range of locations in the dynamic memory could be accomplished. However, in this case, it may be difficult to distinguish a defective or invalid row or column using the tester display because the tester display may lack convenient access to sufficient display resolution.
Without an effective strategy for diagnosing a defective test method, the operator or maintenance personnel may waste time debugging the tester. If the condition is allowed to persist, the tester operator may loose confidence in test results. Poor quality memory devices may be shipped. When test results are unreliable, incorrect yield analysis may lead to incorrect design decisions. Any or all of these effects may eventually erode product profitability.
In the memory testing example above, memory address input signals and memory data input signals are generated by the memory tester according to a logical to physical mapping algorithm. The mapping algorithm may use a table of values or algebraic expressions to express the required translation. If a value in a table is incorrect, a boundary condition of the algebraic expression is incorrect, or a defect exists in the tester electronics that provide the translation function, the memory test will not be fully effective.
There remains a need for a test fixture and test method that can quickly diagnose defects in memory devices and systems, in topologically mapped memory testers, and in topological maps used in memory testing.
A similar problem exists generally for operation and testing of systems which respond to mapped digital signals. In general, a digital signal is mapped to produce a translated or mapped signal when some degree of flexibility or compatibility is required. For example, mapped signals are used to accommodate changing the appearance of graphic information displayed by a computer system and mapped signals are used to accommodate changing peripheral devices in a computer controlled process control system. In each of these cases, there remains a need for a test fixture and test method that can quickly diagnose defects in a source of mapped signals.